In a flip chip packaged integrated circuit, a die containing the integrated circuit has its active side facing a package substrate. Die bumps are soldered to pads on the active side, and are soldered to pads on the package substrate to provide electrical connection between the integrated circuit and the package substrate, as well as to provide a load bearing link between the die and the package substrate. The die bumps form part of the so-called level 1 interconnect, may comprise solder, for example, and may be fabricated by the Controlled Collapse Chip Connection (C4) evaporative bump process. Package contacts on the bottom of the package substrate are electrically coupled to the package substrate pads, forming part of the so-called level 2 interconnect. The package contacts may be solder balls, for example. An underfill is usually applied at the interface between the die and the package substrate to help compensate for the difference in the coefficient of thermal expansion (CTE) between the die and the package substrate.
The die bumps on a die provide power, ground, and I/O (input/output) signals to the integrated circuit. For example, some die bumps serve as a ground connection, some die bumps provide a supply voltage VCC, and some die bumps provide various input and output signals. Many design constraints come into play when determining the number and placement of these types of die bumps in the level 1 interconnect, and the number and placement of package contacts in the level 2 interconnect. One design goal is to reduce the overall inductance, capacitance, and resistance exhibited by these interconnect levels.
Traditionally, it has been difficult to design an integrated circuit package to satisfy a given level of performance unless the level 1 interconnect design has been given. However, integrated circuit designers often desire to evaluate their circuits based on an estimate of package performance before an integrated circuit design has been finalized.
A method by which integrated circuit designers may readily estimate integrated circuit package performance during the early design phase of an integrated circuit has utility.